The present invention relates generally to integrated circuits, and more particularly to an ultra fine pitch I/O designs for microchips.
Advancement of semiconductor processing technology has caused devices implemented in core circuit areas of a microchip to shrink in size. It is estimated that the core circuit area of a particular integrated circuit is reduced by one half as the technology evolves from one generation to the next. Referring to FIG. 1, a floor plan 100 of a microchip manufactured with 90 nm semiconductor processing technology is shown to have a core circuit area 102 where a large number of core devices are implemented and an I/O area 104 where a plurality of I/O devices are disposed. A floor plan 110 of a microchip manufactured with 65 nm technology has a core circuit area 112 and an I/O area 114, and a floor plan 120 of a microchip manufactured with 45 nm technology has a core circuit area 122 and an I/O area 124. These three floor plans 100, 110 and 120 are deigned for implementing the same circuit schematics on semiconductors with various generations of semiconductor processing technology. As shown in the drawing, the core circuit area 112 is about half the size of the core circuit area 102, and the area 122 is about half the size of the area 112.
Although the core circuit areas 102, 112, and 122 continue to shrink in size as the technology evolves, the I/O areas 104, 114 and 124 remain in about the same size, and therefore become the bottleneck for further reducing the size of microchips. One of the reasons that the I/O areas 104, 114 and 124 cannot be further reduced in size is that the pin count of a particular microchip remains unchanged regardless generations of technology. Another reason is that narrowing the width of the I/O areas 104, 114 and 124 can cause the I/O devices to be ineffective in functioning as electrostatic discharge (ESD) protection mechanism. For example, FIG. 2A illustrates three I/O cells 202, 204 and 206 arranged adjacent to each other, forming part of an I/O ring surrounding a core circuit area. Each cell 202, 204 or 206 includes a post-driver NMOS transistor area 208, a post-driver PMOS transistor area 210 and a pre-driver area 212, wherein devices implemented in these areas 208, 210 can function as ESD protection device during an ESD event. FIG. 3A illustrates a cross-sectional view 214 of the devices in the post-driver NMOS transistor area 208 where they function as ESD protection devices. In order for these ESD protection devices to provide a threshold voltage that distinguishes a normal operation state from an ESD protection state, the width D1 of the substrate underlying the polysilicon gates 216 and between ESD pick-up contacts 218 needs to be sufficient in order to provide enough substrate resistance. FIG. 2B shows a layout view of narrowed I/O cells 220, 224, 226, and FIG. 3B shows a cross-sectional view 240 of devices in a post-driver NMOS transistor area 230 in the I/O cell 220. The width D2 of the substrate underlying polysilicon gates 232 and between ESD pick-up contacts 244 is much narrower than D1 shown in FIG. 2A. As a result, this causes insufficient substrate resistance, such that the devices in the post-driver NMOS transistor area 230 cannot function properly as ESD protection devices during an ESD event.
FIG. 4 illustrates another conventional deign that splits I/O cells into two rows 402 and 404 in order to reduce the overall size of the I/O area. However, such design may cause unexpected ESD issues between the two rows of I/O cells, require complex routing of conductive lines, and may not be suitable for ball grid array (BGA) packaging.
As such, what is needed is a layout deign for I/O areas with reduced size in order to allow microchips for further shrinkage as semiconductor processing technology advances.